Tasks and Responsibilities

  • Verify digital logic using SystemVerilog and reusable, standardized methodologies. Verify digital systems that use both custom and standard IP components and interconnects, including microprocessor cores and hierarchical memory subsystems.
  • Contribute to verification and modeling at the chip top level.
  • Debug tests with design engineers to deliver functionally correct design blocks. Work closely with the design and test teams to define test specifications, verification plans and manufacturing transfer.

  • Create and maintain verification infrastructure and tools.
  • Collect and analyze coverage metrics and establish verification best practices.

Requirements

Required title: MSc in Electronic, Electrical, Computer Engineering or relevant field

Required expertise: at least 3 years in similar tasks.

Desirable Competences

Knowledge and Skills

  • Experience in the verification of designs such as transceivers ICs and System on Chip (SoC).
  • Experience with industry-standard simulators, revision control systems and regression systems.
  • Experience with Verilog, SystemVerilog, SVA and functional coverage and working knowledge of makefiles and scripting languages, such as Perl or Python.
  • Experience with verification of low power techniques.
  • Experience with UPF flow.
  • Familiarity with SoC standard interfaces (e.g. AHB, APB) and memory system architectures.
  • Proven software skills

Personal Profile

  • Continuous search for technical excellence,
  • Passion for learning from experience,
  • Critical and constructive attitude,
  • Proactive (problem solving) attitude,
  • Zero bug tolerance,
  • Team membership attitude.

To apply to join the KDPOF team, please send us your CV.