Posts

In collaboration with Ametic, Carlos Pardo will participate in TheMISS Conference, which is accompanying MATELEC trade show.

In collaboration with AMETIC, Carlos Pardo will participate in TheMISS Conference, which is accompanying MATELEC trade show. This leading trade fair for the electrical, electronics, and telecommunications industry is taking place from November 15 to 18, 2022, at IFEMA in Madrid, Spain. On November 18, at 11:30, Carlos will speak about “Spanish and European Proposals to Chip and Semiconductor Shortages” at IFEMA Technology building, Room 3, Pavilion 7. They will discuss strategies and solutions included in PERTE and how companies in Europe are trying to solve the problem locally.
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Integrated KD9351 FOT for automotive gigabit connectivity

Extreme technology, billions of euros and rooms that are much cleaner than those in an operating theater. This is how a microchip is manufactured.

Toñi Fernández from the Spanish radio station Cadena Ser has spoken with KDPOF CEO Carlos Pardo about the plans to set up a semiconductor packaging plant in the Madrid area. As follows, please see the translated summary of the Spanish audio. Read more

V5G Valencia Round Table with Carlos Pardo

In the course of V5G Days from May 30-31 in València, Spain, and online, Carlos Pardo participated in the panel discussion “The Microelectronics Industry in Europe: Recovery or Reinvention?” He summarized the roundtable: “I very much enjoyed the informative talk with representatives from the Spanish semiconductor industry about PERTE, Strategic Projects for Economic Recovery and Transformation in Spain. KDPOF will soon start mass production of semiconductor packaging and testing in Spain of our own products and third parties ones, thanks to IPCEI (Important Project of Common European Interest) and PERTE.”

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Job opening: Senior Mixed-Signal IC Design Engineer

Tasks and Responsibilities

  • Specification of the analog and mixed signal blocks that are embedded in the system (ADC, DAC, PLL, data interfaces, optoelectronics …).
  • Design (from schematic to full verification at extracted level) of the analog and mixed-signal blocks in sub-nanometric CMOS processes. It means being involved in the full AMS design flow: system-level design, schematic, layout and full verification.
  • Definition of layout guidelines for layout engineers and review of their work.
  • Collaboration with the test engineers for the testing definition of the fabricated ICs. Review and analysis of lab characterization data for validation and correlation with simulation results.

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KDPOF on RTVE: Automotive Chips Made in Spain

Report by RTVE: The Madrid-based company KDPOF, based in Tres Cantos, will put chips on the market in 2024. The shortage and the EU’s commitment to attract the technology industry, a business opportunity.

Spanish Company Willing to Manufacture Chips ‘Made in Spain’ in the Midst of Supply Crisis

There is a shortage of chips, that’s a fact. The causes of this supply crisis are diverse: distribution problems stemming from the pandemic, increased demand and even geostrategic issues. But experts agree that one of the most influential factors is the enormous technical complexity behind the manufacture of each chip. Read more