Tasks and Responsibilities
- Implement ASIC / SoCs / FPGAs for multiple products, starting at the specification & design phase, continuing through technology selection, implementation, and validation. Innovation in performance, power and cost to build the best possible product is a must.
- Participate in all phases of ASIC / FPGA design flow (Synthesis, Place & Route, and Timing Closure) as required.
- Work with backend teams to address any layout and timing issues for ASICs.
- Verification by emulation with FPGAs in the lab.
- Involvement in lead-up, validation, characterization and qualification phases of ASICs.
Required title: MSc in Electronics, Electrical, Computer Engineering or relevant field.
Required expertise: at least 4 years in similar tasks.
Knowledge and Skills
- ASIC / FPGA / SoC System integration experience.
- Strong Silicon/ASIC design experience.
- One or more of the following:
- Networking, Wireless, Modem, video CODEC, and Logic design experience.
- Experience with Verilog and System Verilog.
- Experience with latest simulation and verification methodologies (OVM, UVM).
- Experience with EDA tools such as HDL Synthesis (Synopsys DC), HDL simulators (VCS, Questa, IES), HDL Lint tools (Spyglass), FPGA tools (Xilinx Vivado, Altera Quartus II)
- Demonstrated ability to deliver a product from concept to production.
- Demonstrated ability to work in a dynamic environment that includes working with changing needs and requirements.
- Excellent English communication skills both written and verbal.
- Strong software design and skills are nice to have.
- Continuous search for technical excellence,
- Passion for learning from experience,
- Critical and constructive attitude,
- Capability to accept responsibilities from implementation to validation in the laboratory,
- Proactive (problem solving) attitude,
- Rigorous when dealing with production-related information,
- Zero bug tolerance,
- Team membership attitude.
To apply to join the KDPOF team, please send us your CV.